ANALOG 2018 16. GMM/ITG-Fachtagung - MEET YOUR CAD GUY / MEET YOUR DESIGNER - VDE
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PROGRAMM
ANALOG 2018
16. GMM/ITG-Fachtagung
MEET YOUR CAD GUY /
MEET YOUR DESIGNER
13. - 14. September 2018
München/Neubiberg, Am Campeon
12. September 2018
Tu t o r i a l s a m T U M C i t y - C a m p u s
w w w. a n a l o g - f a c h t a g u n g . d e
1
Fachtagung Analog 2018 Inhaltsverzeichnis
Die Fachtagung ANALOG 2018 befasst sich mit allen Teil- Veranstalter und Organisation........................................... 4
gebieten des Entwurfs, der Integration und der Anwendung
Programmkomitee............................................................ 4
analoger, gemischt analog / digitaler und hochfrequenter
Schaltungen und Systeme. Informationen zur Tagung................................................. 5
Homepage ...................................................................... 5
Sie dient dem Informationsaustausch zwischen System-,
Schaltungs- und CAD-Entwicklern, zwischen Industrie, Programm
Forschungseinrichtungen und Hochschulen. Sie vermittelt Mittwoch, 12. September 2018 ....................................... 6
Ideen und Wissen durch Präsentationen von Forschungs-
Tutorials ..................................................................... 6
und Entwicklungsergebnissen sowie durch die Diskussion
von Herausforderungen und Lösungsansätzen. Dabei weist Analogfachgruppentreffen .......................................... 6
sie gleichzeitig auf Lücken und ungelöste Aufgaben hin.
Donnerstag, 13. September 2018 ................................. 10
Die Fachtagung ist auch ein ausgezeichnetes Instrument Eingeladener Vortrag J. Sauerer ….................... 10 / 24
zur Unterstützung des Ergebnistransfers bei öffentlich ge-
Eingeladener Vortrag M. Ivanov …..................... 11 / 26
förderten Forschungs- und Entwicklungsprojekten.
Eingeladener Vortrag R. Findenig/G. Rutsch ….. 11 / 28
Insbesondere werden der wissenschaftliche Nachwuchs Postersession ................................................... 11 / 16
und junge Entwicklungsingenieure ihre auch in einem
frühen Stadium befindlichen Forschungs- und Entwick-
Freitag, 14. September 2018.......................................... 13
lungsarbeiten präsentieren. Eingeladener Vortrag T. Gossmann/J. M. Tomasik .13 / 30
Postersession ................................................... 13 / 16
Die Tagungssprache ist Deutsch, etliche Vorträge werden
in Englisch sein. Eingeladener Vortrag V. Issakov ........................ 14 / 32
Eingeladener Vortrag W. Hartong, A. Schaldenbrand,
Ein besonderes Anliegen der ANALOG 2018 ist der
V. Zivkovic ......................................................... 14 / 34
Austausch zwischen Schaltungsentwicklung und CAD-
Entwicklung. Die ANALOG 2018 steht daher unter dem Allgemeine Hinweise....................................................... 36
Motto
Tagungsorganisation................................................. 36
MEET YOUR CAD GUY/MEET YOUR DESIGNER Anmeldung............................................................... 36
Teilnahmegebühren................................................... 36
Lassen Sie sich von diesem Motto und vom Standort
Campeon in München-Neubiberg zum Besuch anregen! Stornierung............................................................... 37
Telefonische Erreichbarkeit während der Tagung....... 37
Ihr Organisations-Team der Analog 2018 Tagungsort ............................................................... 37
Zimmerreservierungen.............................................. 38
Abendveranstaltung ................................................. 39
2 3
Veranstalter und Organisation T. Reich Fraunhofer-Institut für Integrierte Schaltungen
IIS, Dresden
VDE/VDI-Gesellschaft Mikroelektronik, Mikrosystem- und
Feinwerktechnik (GMM) S. Sattler Friedrich-Alexander-Universität Erlangen-
Nürnberg
Informationstechnische Gesellschaft im VDE (ITG) J. Scheible Hochschule Reutlingen
R. Thewes Technische Universität Berlin
T. Ußmüller Universität Innsbruck
Tagungsleitung und Vorsitzender des
Programmkomitees R. Weigel Friedrich-Alexander-Universität Erlangen-
Nürnberg
Helmut Gräb Technische Universität München
Organisationsteam
Programmkomitee
H. Gräb Technische Universität München
J. Anders Universität Stuttgart C. Grimm Technische Universität Kaiserslautern
T. Gemmeke RWTH Aachen K. Hahn Universität Siegen
C. Grimm Technische Universität Kaiserslautern J. Kampe Ernst-Abbe-Hochschule Jena
K. Hahn Universität Siegen M. Olbrich Gottfried Wilhelm Leibniz Universität
W. Hartong Cadence Design Systems GmbH, Hannover
Feldkirchen R. Popp edacentrum Hannover
L. Hedrich Johann Wolfgang Goethe-Universität R. Schnabel VDE/VDI-GMM, Frankfurt am Main
Frankfurt am Main
E. Hennig Hochschule Reutlingen
K. Hofmann TU Darmstadt Informationen zur Tagung
J. Kampe Ernst-Abbe-Hochschule Jena Website: www.analog-fachtagung.de
D. Killat Brandenburgische Technische Universität
Cottbus-Senftenberg VDE/VDI-Gesellschaft Mikroelektronik, Mikrosystem- und
D. Kissinger IHP Leibniz-Institut für innovative Mikroelek- Feinwerktechnik (GMM)
tronik
Ansprechpartner
M. Kuhl Albert-Ludwigs-Universität Freiburg - IMTEK
C. Lang Melexis GmbH, Erfurt Dr.-Ing. Ronald Schnabel
J. Lienig Technische Universität Dresden Stresemannallee 15
Y. Manoli Albert-Ludwigs-Universität Freiburg- IMTEK 60596 Frankfurt
Telefon: 069 / 6308 - 227, -360
W. Mathis Gottfried Wilhelm Leibniz Universität
Telefax: 069 / 6308 - 9828
Hannover
E-Mail: gmm@vde.com
M. Olbrich Gottfried Wilhelm Leibniz Universität
Hannover
S. Paul Universität Bremen
R. Popp edacentrum GmbH, Hannover
H. Pretl Intel/ Johannes Kepler Universität Linz
C. Zivkovic Technische Universität Kaiserslautern
4 5
■ Mittwoch, 12. September 2018 ■ ANALOG 2018 – Tutorials
P R O G R A M M Z U R FA C H TA G U N G Tutorial A: „Analog Coverage – Yesterday‘s Dreams,
Today‘s Reality and Tomorrow‘s Capabilities“
ANALOG 2018
Walter Hartong, Cadence, Munich, Germany;
Lars Hedrich, University of Frankfurt, Frankfurt/Main,
Mittwoch, 12. September 2018
Germany;
Technische Universität München, Markus Olbrich, University of Hanover, Hannover, Germany
Arcisstraße 21, Analog circuits are constantly growing in complexity.
80333 München,
Seminarraum 2999 Hence, the verification environment needs to include
various input voltages, output loads, temperature ranges
or process variations. Many special verification tasks are
13:00 Registrierung, Kaffee mandatory, like statistical analysis, EM/IR, reliability analy-
sis, post layout simulation.
Tutorials Simultaneously, the requirements on verification quality
are increasing drastically – the ISO26262 norm for auto-
motive is the most popular example in this trend. The time
13:30 Tutorial A: Analog Coverage - Yesterday‘s
to market pressure requires even the consumer market to
Dreams, Today‘s Reality and Tomorrow‘s
demand strict verification quality goals. A re-spin of a large
Capabilities
Walter Hartong, Cadence, Munich, Germany SOC due to an analog failure is not acceptable anymore.
Lars Hedrich, University of Frankfurt, Frankfurt/ Beside the classical interactive verification approach, more
Main, Germany formalized techniques, verification planning, and complete-
Markus Olbrich, University of Hanover, Hannover, ness and quality metrics are required. Here the concept of
Germany
„verification coverage“ can help to enhance the verification
16:00 Tutorial B: Advances in Worst Case and Yield quality and efficiency.
Analysis for Circuit Design In this tutorial, we will present the latest trends from the
Michael Pronath, MunEDA, Munich, Germany EDA industry, namely Cadence Virtuoso ADE Verifier with
its new capability to do coverage driven verification for ana-
17:15 Ende
log circuit. We will see how this can be used in re-live pro-
jects even today.
17:30 Analogfachgruppentreffen
In addition, the academic driven view on analog coverage
is presented. The latter stems in parts from the ANCONA
project focusing on analog coverage approaches.
Main part of the tutorial will be live demos and hands-on
experience in the context of possible coverage measures,
a practical view on existing measures and methodologies.
Some new approaches to measure coverage and combine
the results in an overall coverage view. The whole tutori-
al will be accompanied by concrete results on small and
middle size examples circuits.
6 7
■ ANALOG 2018 – Tutorials ■ ANALOG 2018 – Tutorials
Walter Hartong studied Electrical Engi- Tutorial B: „Advances in Worst Case and Yield
neering/Microelectronics at the Universi- Analysis for Circuit Design“
ty of Hannover.
He worked as a research assistant at the Michael Pronath, MunEDA, Munich, Germany
Institute of Microelectronic Systems and In this tutorial we will review a statistical worst case analysis
finished his PhD in Computer Science in methodology for designers of analog/RF/digital full custom
2002. circuits, which includes operating conditions such as tem-
Since 2002, he has been with Cadence Design Systems in perature or Vdd, aging, as well as random variation of the
Munich, initially as application engineer. His current role is manufacturing process.
Product Engineering Architect focusing on analog simulati-
We will discuss its mathematical background, accuracy and
on environment and verification.
efficiency, demonstrate recent algorithmic improvements of
He is one of the core drivers in the ADE Verifier develop- worst case analysis software, together with applications of
ment and contributes to Explorer and Assembler as well. high sigma statistical analysis to analog/RF circuits and to
Walter is also interested in mixed-signal topics, analog fault large regular circuit structures such as memory arrays.
simulation and behavioral modeling.
Michael Pronath has extensive expe-
Lars Hedrich received the Diploma
rience in statistical analysis, modeling,
degree in electrical engineering in 1992
and optimization.
and the Ph.D. in 1997 from the University
of Hannover and became a junior profes- Prior to founding MunEDA, Michael
sor at the same University in 2002. worked as a research assistant at the
Since 2004 he has been full professor Institute for Electronic Design Automation
at the Institute of Computer-Science, at the Technical University of Munich.
University of Frankfurt, and head of the He holds a PhD in Electrical Engineering from the Techni-
design methodology group at the same institute. cal University of Munich as well as an MBA of University of
His research interests include several areas of analog de- Hagen.
sign automation: symbolic analysis of linear and nonlinear Dr. Pronath is author and coauthor of several international
circuits, behavioral modeling, reliability analysis and design, publications on methods of analog integrated circuit design
circuit synthesis, and formal verification. and testing of mixed-signal circuits.
Markus Olbrich received his Dipl.-Ing.
and Dr.-Ing. degrees from Leibniz Uni-
versity of Hannover in 1996 and 2005,
respectively.
He is now with the Institute of Microelec-
tronic Systems in Hannover as group
leader since 2001 and Academic Direc-
tor since 2010.
His research interests cover mixed-signal verification me-
thods including formal verification and he also works on
physical design methods.
8 9
■ Donnerstag, 13. September 2018 ■ Donnerstag, 13. September 2018
Donnerstag, 13. September 2018 11:45 Mittagessen/Postersession
Am Campeon 1-12, 13:00 Eingeladener Vortrag (siehe Seite 26)
85579 Neubiberg Moderator: Roland Thewes TU Berlin
Konferenzzone im Gebäude 02
Current Sensing Circuits and Applications
Misha Ivanov, Texas Instruments Deutschland
GmbH
08:15 Registrierung, Kaffee
08:45 Begrüßung, Verleihung Best Paper Award 13:45 Session 2: ADC, DAC, PLL
Helmut Gräb, TU München
Moderator: Carna Zivkovic, TU Kaiserslautern
09:00 Eingeladener Vortrag (siehe Seite 24)
Moderator: Markus Olbrich, Leibniz Universität Ultra-Low-Power SAR ADC in 22 nm FD-SOI
Hannover Technology Using Body-Biasing
Marcel Jotschke, Sunil Satish Rao, Benjamin
Cognitive Sensing: What Does This Mean for
Prautsch, Torsten Reich, Fraunhofer IIS/EAS Dres-
Us?
den
Josef Sauerer, Fraunhofer-Institute for Integrated
Circuits IIS, Erlangen A Reusable Triple Core 12-bit Current Stee-
ring Digital-to-Analog Converter for High-
09:45 Kurzvorstellung Poster
Performance Transceivers in Industry 4.0
Moderator: Helmut Gräb, TU München
Applications
10:15 Kaffee/Postersession Reimund Wittmann, Jan Steinkamp, Frank Henkel,
IMST GmbH Kamp-Lintfort, Klaus Tittelbach-
10:45 Session 1: Sensoren Helmrich, IHP, Andreas Wolf, Dr. Wolf Wireless
GmbH
Moderator: Torsten Reich, Fraunhofer IIS/EAS
Design of a 28-32 GHz Low-Noise PLL with
Front-End für Long-Range-UHF-RFID- Automatic Frequency Calibration
Sensortags mit einer Empfindlichkeit von Frank Herzel, Arzu Ergintav, Ulrich Jagdhold,
-30 dBm Dietmar Kissinger, IHP GmbH Leibniz-Institut für
Jacek Nowak, Dominik Krausse, Ralf Sommer, TU innovative Mikroelektronik, Frankfurt/Oder
Ilmenau
Design of a High Accuracy Spatially Distri- 14:45 Pause
buted Temperature Sensor Array for CMOS
Lab-on Chip Applications 15:00 Eingeladener Vortrag (siehe Seite 28)
Yvonne Ebensberger, Timo Lausen, Roland Thewes, Moderator: Jens Lienig, TU Dresden
TU Berlin Behavioural Modeling for SoC Simulation:
Design of Quasi-Synchronous Finite Sta- Bridging Analog and Firmware Demands
te Machines Using a Local On-Demand Rainer Findenig, Gabriel Rutsch, Infineon Techno-
Clocking Approach logies AG
Athanasios Gatzastras, Dominik Wrana, Tobias
Wolfer, HS Reutlingen, Georg Gläser, Benjamin 15:45 Kaffee/Postersession (siehe Seite 16)
Saft, Eric Schäfer, IMMS Institut für Mikroelek
tronik- und Mechatronik-Systeme gemeinnützige
GmbH, Eckhard Hennig, HS Reutlingen
10 11
■ Donnerstag, 13. September 2018 ■ Freitag, 14. September 2018
16:15 Session 3: Verifikation Freitag, 14. September 2018
Moderator: Eckhard Hennig, HS Reutlingen
Am Campeon 1-12,
Coverage Measures and a Unified Coverage 85579 Neubiberg
Model for Analog Circuit Design Konferenzzone im Gebäude 02
Andreas Fürtig, Goethe-Universität Frankfurt a. M.,
Walter Hartong, Cadence Design Systems, Lars
Hedrich, Goethe-Universität Frankfurt a. M., Mar- 08:30 Registrierung, Kaffee
kus Olbrich, Malgorzata Rechmal, Leibniz Univer-
sität Hannover, Louis-Francois Tanguay, Cadence 09:00 Eingeladener Vortrag (siehe Seite 30)
Design Systems Moderator: Thomas Ußmüller, Universität Innsbruck
Verification of Analog/Mixed-Signal Systems Competitive CMOS RF Transceiver Design
with AADD Timo Gossmann, Jakob M. Tomasik, Intel
Carna Zivkovic, Christoph Grimm, TU Kaiserslautern Deutschland GmbH
Automatic Abstraction of Analog Circuits to
Hybrid Automata
Ahmad Tarraf, Lars Hedrich, Goethe-Universität 09:45 Session 4: Advanced CMOS
Frankfurt a. M. Moderator: Matthias Kuhl, TU Hamburg-Harburg
17:15 Panel: The Design Productivity Gap has been Low-Power 24 GHz LNA in a Sub-28nm CMOS
Growing for 20 Years – Who Cares? Vadim Issakov, Radu Ciocoveanu, Andreas Wert-
hof, Infineon Technologies AG, Robert Weigel,
Moderator: Klaus Hofmann, TU Darmstadt
Friedrich-Alexander Universität Erlangen-Nürnberg
Panelists: (siehe Seite 20 - 23)
Comparison and Optimization of the Minimum
Dave Reed, Synopsys Supply Voltage of Schmitt Trigger Gates versus
Klaus Cerny, Cadence Design Systems CMOS Gates under Process Variations
Vadim Issakov, Infineon Technologies, Neubiberg Alexander Bleitner, Jacob Goeppert, Niklas Lotze,
Dietmar Kissinger, IHP Frankfurt/Oder Matthias Keller, Yiannos Manoli, IMTEK Albert-
Ulrich Nerz, Infineon Technologies, Neubiberg Ludwigs-Universität Freiburg
18:15 Ende des Panels Analysis and Optimization of Voltage Refe-
rence Circuits Based on Sub 1V MOSFETs
19:30 Abendveranstaltung im Donisl, Traditions- Operating in Different CMOS Technologies
wirtshaus am Marienplatz Giuseppe Quarata, Michael Pronath, MunEDA
GmbH München
22:00 Ende des ersten Veranstaltungstages
10:45 Kaffee/Postersession (siehe Seite 16)
12 13
■ Freitag, 14. September 2018 ■ Freitag, 14. September 2018
11:15 Eingeladener Vortrag (siehe Seite 32) 15:15 Session 6: Licht & Zufall
Moderator: Thomas Gemmeke, RWTH Aachen
Moderator: Helmut Gräb, TU München
Design Challenges and Methodology Con-
siderations for Highly Integrated mm-Wave Design of an Automotive Visible Light Com-
Systems in Silicon-Based Technologies munications Link Using an Off-The-Shelf LED
Vadim Issakov, Infineon Technologies Headlight
Stephan Kruse, Christian Kress, Heinz Nixdorf
12:00 Mittagessen/Postersession Institut Universität Paderborn, Claas Tebruegge,
HELLA GmbH & Co. KGaA, Agon Memedi,
13:00 Eingeladener Vortrag (siehe Seite 34) Muhammad Sohaib Amjad, Christoph Scheytt
Moderator: Eckhard Hennig, HS Reutlingen Falko Dressler, Heinz Nixdorf Institut Universität
Paderborn
Improving Test Coverage and Eliminating
Test Escapes Using Analog Defect Analysis Ringoszillator-basierender Ultra-Low-Power-
Walter Hartong, Art Schaldenbrand, Zufallszahlengenerator für passive UHF RFID
Vladimir Zivkovic, Cadence Design Systems Transponder
Georg Saxl, Manuel Ferdik, Thomas Ußmüller,
13:45 Session 5: Synthese & Layout Universität Innsbruck
Moderator: Jürgen Scheible, Robert Bosch Zentrum für On-Line Parameter Extraction Technique for
Leistungselektronik, HS Reutlingen Integrated Circuits
Theodor Hillebrand, Konstantin Tscherkaschin,
On Applying Pareto Optimization for Complete Steffen Paul, Dagmar Peters-Drolshagen, Univer-
Performance Space Modeling of Analog ICs sität Bremen
David Schreiber, Jürgen Kampe, Ernst-Abbe-
Hochschule Jena 16:00 Schlusswort
Template-Driven Analog Layout Generators Helmut Gräb, Technische Universität München
for Improved Technology Independence
Benjamin Prautsch, Uwe Hatnik, Uwe Eichler, 16:15 Ende der Tagung
Fraunhofer IIS/EAS Dresden, Jens Lienig, TU
Dresden
Automatic Analog-on-top Chip-Level Sche-
matic Generation Based on Wire-by-Name
Methodology
Jürgen Wittmann, Carsten Wegener, Fabio Rigoni,
Dialog Semiconductor GmbH
14:45 Kaffee
14 15
■ ANALOG 2018 – Poster ■ ANALOG 2018 – Poster
Poster Session 2: ADC, DAC, PLL und mehr
Session 1: Sensoren P2.1 Einfluss der Taktratensteuerung auf die Ge-
nauigkeit asynchroner ADCs
P1.1 Enhanced Behavioral Models of MEMS Ele- Pavol Pitonak, Dirk Killat, Haoran Zhu, BTU
ments for the System Level Verification Cottbus-Senftenberg
Tino Blochmann, Stephan Gerth, Peter Schneider,
Roland Jancke, Fraunhofer IIS/EAS Dresden P2.2 Induktive Vernetzung von Hörgeräten
Jan-Christoph Edelmann, Thomas Ußmüller,
P1.2 Effizientes Design und Layout von 3D-Be- Universität Innsbruck
schleunigungssensoren mittels automatisier-
ter Synthese P2.3 Akustische Übertragung medizinischer Daten
Steffen Michael, Maria Kellner, Ralf Sommer, über die Sprechanlage eines MRT
IMMS GmbH Viktoria Kalpen, Thomas Ußmüller, Universität
Innsbruck
P1.3 Online Surveillance Techniques for Reliable
Active Pixel Sensor Systems P2.4 UHF-RFID-Lesegerät basierend auf der NI
Theodor Hillebrand, Konstantin Tscherkaschin, PXIe Plattform
Sebastian Schmale, Steffen Paul, Dagmar Peters- Manuel Ferdik, Markus Samuel Hesche, Lars-Oliver
Drolshagen, Universität Bremen Rack, Georg Saxl, Thomas Ußmüller, Universität
Innsbruck
P1.4 Entwurf und Implementierung eines Sensor-
netzwerks zur Baustellensicherung mittels
LPWAN Session 3: Verifikation, Simulation, Modelllierung
David Krönert, Kai Hahn, Universität Siegen, Helmut
Kremer, micro-part GmbH&Co.is.KG, Gunnar P3.1 Fehlersuche innerhalb des μ-Controllers vom
Monheimius, TAMMET Systems International Typ PIC32MX
GmbH Farouk Babba, Sebastian Sattler, Friedrich-Alexan-
der Universität Erlangen-Nürnberg
P1.5 Ein integrierter Schaltkreis zur chronischen
Aufnahme von Hirnsignalen bei neugebore- P3.2 Transistor-Level Simulation of LC-tank VCO
nen Mäusen Electron Spin Resonance Detectors
Andreas Bahr, Universität Kiel Anh Chu, Benedikt Schlecker, Jens Anders,
Universität Stuttgart
P3.3 A Hierarchical Method to Perform IR Drop
and Electromigration Analysis for Faster
Tape-out of Analog-on-top Designs
Tarjina Islam, Infineon Technologies AG
P3.4 Modeling of Delta-Sigma Modulators for
Low-Power Audio Applications
Ciana Barretto, Elmar Herzer, Akshay Agashe,
Johann Hauer, Fraunhofer-Institut für Integrierte
Schaltungen IIS Erlangen, Mirco Meiners, Hoch-
schule Bremen
16 17
■ ANALOG 2018 – Poster ■ ANALOG 2018 – Poster
Session 4: Advanced CMOS Session 5: Synthese & Layout
P4.1 Theoretical Derivation of Bandwidth Limits P5.1 Entwurf von zeitkontinuierlichen Sigma-Delta
of a Symmetric Acoustic-Wave Lumped-Ele- Modulatoren mit www.sigma-delta.de
ment Resonator (AWLR) Module Johannes Wagner, Maurits Ortmanns, Universität
Michael Wagner, Friedrich-Alexander Universität Ulm
Erlangen-Nürnberg, Stephan Leuschner, Intel
Deutschland GmbH, Robert Weigel, Amelie Ha- P5.1 Parallelization Strategies for the Detailed
gelauer, Friedrich-Alexander Universität Erlangen- Routing Step
Nürnberg Björn Bredthauer, Markus Olbrich, Erich Barke,
Leibniz Universität Hannover
P4.2 Design of an EMC-Improved Regulated Charge
Pump in 180-nm CMOS Technology P5.3 A Procedural Approach to Automate the
Dirk Nuernbergk, Christian Lang, Viktor Petri, Manual Design Process in Analog Integrated
Michael Frey, Melexis GmbH Circuit Design
Florian Leber and Jürgen Scheible, Robert Bosch
P4.3 Considerations on the Design Methodology Zentrum für Leistungselektronik, HS Reutlingen
for an Integrated Gate Driver
Norbert Fiebig, Gunter Fischer, Pylyp Ostrovskyy, P5.4 Design Methodologies and Co-Design Options
Dietmar Kissinger, IHP GmbH Leibniz-Institut für for Novel 3D Technologies
innovative Mikroelektronik Tilman Horst, Robert Fischbach, Jens Lienig,
TU Dresden
P4.4 Ultra-Low-Power Self-Biased 1 nA Current
Reference Circuit for Medical Monito-
ring Devices in 350 nm and 180 nm CMOS Session 6: Licht & Zufall
Technology
P6.1 Methoden zur Verbesserung von CMOS inte-
Gayas Mohiuddin Sayed, Pablo Mendoza-
grierten Arbiter-PUFs
Ponce, Wolfgang Krautschneider, Matthias
Andreas Herkle, Joachim Becker, Maurits Ortmanns,
Kuhl,Technische Universität Hamburg-Harburg
Universität Ulm
P4.5 Content-Addressable Memory – Trends and
Outlook of an Enabler for Modern-Day Appli-
cations
Xin Fan, Amgad Ghonem, Tobias Gemmeke,
RWTH Aachen
P4.6 A CMOS Bidirectional -69 mA to +63 mA
Output Range Voltage-Controlled Current
Source for Laser Diode Current Control in
FTTx Applications
Sreekesh Lakshminarayanan, Jing Ning, Klaus
Hofmann, TU Darmstadt
18 19■ ANALOG 2018 – Panel ■ ANALOG 2018 – Panel
Panel: The Design Productivity Gap has been Technology he overviews the EDA development trends and
Growing for 20 Years – Who Cares? market needs in the Custom IC design space.
The costs for the development of mixed-signal circuits have Before joining Cadence he held various IC design and pro-
increased enormously for years. The development metho- ject management positions for LCD TV/Monitor products
dology is actually still like 20 years ago. Most of the aca- in Philips Semiconductor and Server Systems in Siemens
demic papers are about smaller, better and faster circuits. Nixdorf AG.
Hardly anyone ever imagines how to develop a circuit of
certain complexity with half the effort. Although the metho-
dology papers address some efficiency issues, their practi- Vadim Issakov was born in the Russian
cal implementation is lacking.“ (Anonymous) Federation in 1981
This panel will discuss if this is statement is (still) valid, and He received M.Sc. degree (cum laude) in
if yes, why it is valid and if remedy is close. Where are the microwave engineering from the Techni-
gaps and needs of AMS system design in details, what can cal University of Munich and Ph.D. de-
EDA do now and in future? gree from the University of Paderborn,
Germany (summa cum laude) in 2006
and 2010, respectively.
Panelists:
He is a principal engineer for mm-wave circuit design at
Infineon Technologies AG in Neubiberg, Germany. He is a
Dave Reed is director of marketing for
technical lead of a research group working on mm-wave
custom design tools at Synopsys. He
circuit design in CMOS and SiGe technologies for radar and
has been involved in IC design and elec-
communication applications.
tronic design automation for more 30
years, with a focus on analog and cus-
tom design. He joined Synopsys through
Dietmar Kissinger (S’08–M’11–SM’14)
the acquisition of SpringSoft. Before
received the Dipl.-Ing., Dr.-Ing. and habil.
SpringSoft, Dave was co-founder and
degree in electrical engineering from FAU
CEO of Blaze DFM, which helped customers overcome de-
Erlangen-Nürnberg, Germany, in 2007,
sign challenges of advanced process nodes. Prior to Blaze
2011 and 2014, respectively.
Dave was VP of Marketing at Monterey Design. Dave holds
a BS in Electrical Engineering from Lehigh University. From 2007 to 2010, he was with Da-
nube Integrated Circuit Engineering,
Linz, Austria, where he worked as a System and Applica-
Klaus Cerny studied Electrical Enginee- tion Engineer in the Automotive Radar Group. From 2010
ring at the University of Applied Science to 2014, he held a position as Lecturer and Head of the
in Augsburg and Economics at the Uni- Radio Frequency Integrated Sensors Group at the Insti-
versity of Hagen. tute for Electronics Engineering, Erlangen. Since 2015,
he has been a Full Professor at the Technische Universi-
He is with Cadence since 2006 and in
tät Berlin and the Head of the Circuit Design Department
his role as Senior Account Manager
at IHP, Frankfurt (Oder). His current research interests in-
20 21■ ANALOG 2018 – Panel ■ ANALOG 2018 – Panel
clude silicon high-frequency and high-speed as well as Ulrich Nerz was born 1957 in Reutlin-
low-power integrated systems for communication and gen, Germany and has more than 30
automotive, industrial, security and biomedical sensing
years of experience in semiconductor
applications. He has authored or co-authored over 250
development in Siemens and Infineon.
technical papers and holds several patents.
He started in the EDA department to in-
Dr. Kissinger is a member of the European Microwave As- troduce first P&R tools, develop libraries
sociation (EuMA) and the German Information Technology and RAM-generators to support the
Society (ITG) and Society of Microelectronics, Microsystems change from full custom to semicustom design.
and Precision Engineering (VDE/VDI GMM). He currently
In 1994 he changed to Microcontroller development being
serves as a member of the technical program committee of
responsible for the 16 bit product development for automo-
the European Solid-State Circuits Conference (ESSCIRC),
tive and industrial applications
a member of the technical program committee of the IEEE
MTT-S International Microwave Symposium (IMS), and as In the years that followed he held various management
the Chair of the Executive Committee of the IEEE Radio positions in Microcontroller R&D.
and Wireless Week (RWW). He was a two-time Chair of
Since 2010 he has been one of the key persons being
the IEEE Topical Conference on Wireless Sensors and Sen-
responsible for the development of Infineon’s 32bit AURIX
sor Networks (WiSNet) and a two-time Chair of the IEEE
Microcontroller family which is successfully used in many
Topical Conference on Biomedical Wireless Technologies,
car applications such as power train, chassis, safety and
Networks and Sensing Systems (BioWireless). He further
autonomous driving.
served as a member of the 2013 and 2017 European Mi-
crowave Week (EuMW) Organizing Committee and as
member of the 2018 IEEE MTT-S International Microwave Moderator:
Symposium (IMS) Steering Committee. He was a nine-time Klaus Hofmann is a full professor at TU
Guest Editor for the IEEE Microwave Magazine and served Darmstadt holding a Dipl.-Ing. Degree in
as an Associate Editor for the IEEE Transactions on Micro- Electrical Engineering (1992) from Ruhr-
wave Theory and Techniques. He was the Chair of the IEEE University Bochum, Germany, and recei-
MTT-S Technical Committee on Microwave and Millimeter- ved the Ph.D.degree from TU Darmstadt
Wave Integrated Circuits (MTT-6) and is currently an elected in 1997. From 1998 to Feb. 2009 he was
member of the IEEE MTT-S Administrative Committee. He with Siemens AG, Infineon Technologies
received the 2017 IEEE MTT-S Outstanding Young Engi- AG and Qimonda AG in various positions
neer Award, the 2017 VDE/VDI GMM-Prize, and was the (last position: director product development), such as lea-
co-recipient of nine best paper awards. ding the “Advanced Technology Software” and a product
development department designing DDR-DDR3 DRAM
products ranging from90nm downto 65nm technologies.
From 2009 on he is heading the Integrated Electronic
Systems Lab of TU Darmstadt as full professor with re-
search interests in Analog and Digital Integrated Circuits
and Systems, Integrated High Voltage Circuits, Application
of Integrated Circuits in robust environments (Industrie 4.0,
Infrastructure, FAIR) and Printed Electronics.
22 23■ ANALOG 2018 – Invited Talks ■ ANALOG 2018 – Invited Talks
Cognitive Sensing: What Does this Mean for Us? Josef Sauerer received his diploma
in electrical engineering from Friedrich
Presenter: Josef Sauerer, Fraunhofer-Institute for Integrated
Alexander University Erlangen Nurem-
Circuits IIS, Erlangen
berg in 1985.
In many today’s applications we have smart or intelligent He started his professional career as
sensors, more complex systems comprising the primary analog IC designer at the Fraunhofer
sensing element, analog circuitries i.e. for excitation con- Institute for Integrated Circuits IIS in
trol, compensation and analog signal conditioning, analog- Erlangen. For some years he was leading a group desig-
to digital converter, digital information processing and di- ning fast analog-to-digital converters in III/V technologies.
gital communication interface. They often provide support In 1993 he became head of the department for analog
for various modes of operation and interfacing and can IC design with main focus on development of mixed signal
take some predefined actions or calculations. Smart sen- ASICs for industrial and automotive applications. For some
sors can locally extract information from measured input years he was responsible for all IC-design activities at
data and transmit the information when necessary, thus Fraunhofer IIS covering CMOS integrated sensor systems,
reducing network requirements and complexity of central RF-ICs, mixed signal ICs and digital Ics.
processing units. Cognitive sensors deploy a number of dif-
Currently Josef Sauerer is heading the division of Smart
ferent input values for acquiring situated information of the
Sensing and Electronics comprising IC design, optical and
sensed environment. They are equipped with additional ca-
hall-sensor systems, imaging systems and medical tech-
pabilities based on machine learning processes. This enab-
nologies.
les cognitive sensors to build up empirical knowledge from
their environment. They can work out particular patterns
and trends from the signals. Cognitive sensor systems do
not just capture measurement values. They analyze them
directly, take decisions locally by intelligent interpretations
and decide when it is necessary to pass on information or
to trigger actions locally.
Thus, cognitive sensing extends »intelligent sensors« by
employing sensor fusion and machine learning approaches
to solve complex sensing tasks and to bring sensed infor-
mation in a context.
This presentation will give examples of how cognitive sen-
sor systems enable digital transformation to be realized in
different application areas: Self-learning approaches can
extend possibilities in magnetic position sensing; multimo-
dal sensor fusion combined with machine learning based
data evaluation helps properly brushing teeth, analyzing a
driver’s emotions or even enabling a digital representation
of human sensory perceptions.
24 25■ ANALOG 2018 – Invited Talks ■ ANALOG 2018 – Invited Talks
Current Sensing Circuits and Applications Misha Ivanov holds an M.S.E.E. degree
from Ohio State University and has been
Presenter: Misha Ivanov, Texas Instruments Deutschland
with Burr-Brown and Texas Instruments
GmbH, Freising
since 1997, first in Arizona and from
Today, we need to measure current everywhere. In most, if 2001 in Germany.
not all electrical systems, it is a key part of managing power.
Misha has designed precision linear and
However, the requirements to the measurement of current
mixed signal amplifiers, sensor conditio-
have vast variation. We need to sense leakages in micro-
ning circuits and delta-sigma modulators.
amps, get to full scale in 100’s of amps, at speed up to
1MHz and the potentials of the current conductor that jump He holds sixteen patents and was elected TI‘s Senior
from 0V to 600V in■ ANALOG 2018 – Invited Talks ■ ANALOG 2018 – Invited Talks
Behavioural Modeling for SoC Simulation: Gabriel Rutsch received an MSc degree
Bridging Analog and Firmware Demands in Electrical and Computer Enginee-
ring from Technical University Munich in
Presenter: Rainer Findenig, Gabriel Rutsch, Infineon Tech-
2015.
nologies AG
Since then he has been working for Infi-
Simulating today’s SoC models requires fast models of the
neon Technologies AG as methodology
digital part, the compute platform, and the analog part, in
development and system level design
order to be able to efficiently run application software in the
engineer.
simulation.
His specific field of activity is the methodology development
While abstraction for digital models is well understood, our
for AMS system modeling and emulation.
experience shows that today, the most critical issues are
with analog models.
A sensible abstraction is required to achieve models that
include all relevant details with the required accuracy, yet
still provide the simulation performance required for SoC
and firmware verification. At the same time, to reduce de-
velopment costs, additional focus needs to be placed on
maintainability and reusability. In this talk, we show how we
addressed this challenge for different SoCs developed at
Infineon.
Rainer Findenig received his diploma
from the Upper Austrian University of
Applied Sciences in Hardware/ Software
Systems Engineering in 2007 and his
PhD from Johannes Kepler University
Linz in 2016.
His PhD research was focused on code
generation for efficient models of digital hardware for virtual
prototyping.
He joined Infineon in 2016 and is currently in charge of
virtual prototype development for Infineon’s high-end
Radar Ics.
28 29■ ANALOG 2018 – Invited Talks ■ ANALOG 2018 – Invited Talks
Competitive CMOS RF Transceiver Design Lacking some required ingredients for the assigned work
packages, he became also involved in synthesis library
Presenter: Timo Gossmann, Jakob M. Tomasik, Intel
development and design flow topics.In 1997 he joined
Deutschland GmbH, Munich
SIEMENS semiconductor RF design group, extending his
The evolution of modern systems for cellular communi- CMOS/digital-centric expertise towards BiCMOS technolo-
cation started with GSM is currently moving towards 5G. gies, RF- and mixed signal design.
This is also reflected in the evolution of Intel’s SMARTi(TM)
After initially working on car radio applications, he soon
transceiver ICs. Since starting in 2000, our SMARTi-pro-
transitioned to cellular product development, right before
duct family has seen a significant transformation in techno-
the SMARTi cellular RF transceiver product line activities
logy, architecture, die size, supported bands and features.
were started.
To keep pace and to cope with these ever increasing
demands, our development process had to be adapted Since then he actively contributed to design and producti-
and optimized, new methodologies and tools had to be zation of many SMARTi versions throughout the years with
developed and very different engineering mindsets had to SIEMENS, Infineon and currently Intel.
be aligned. This does not end now, next generation RF
He also e also held several technical lead and line manage-
transceivers will set even more demanding challenges to
ment positions in Germany and several foreign countries
comply with requests to meet more stringent KPIs.
and is currently leading the transmitter sub-project in the
In this talk, we will give an impression about the comple- next ramping high volume product.
xity of a state of the art cellular transceiver chip. We will
show what kind of engineering resources and disciplines
(e.g. analog, digital, RF and software design) are involved Jakob M. Tomasik received his diploma
and why their tight cooperation is necessary to map the and his PhD degree from the Hamburg
extremely complex requirements to a successful product University of Technology (TUHH) in 2004
operated in modern cellular phones. and 2010, respectively.
His PhD topic was focused on the re-
search of low-noise and low-power ana-
Timo Gossmann received his diploma
log circuits for biomedical applications.
in electrical engineering from TU Darm-
stadt in 1995. From 2010 to 2013 he worked as an R&D engineer at
EPCOS GmbH & Co. KG, Duisburg, on automotive and
As student he was working at Panaso-
industrial microcontroller solutions. In 2013, he joined Intel
nic and worked on the first 100Hz digital
Deutschland GmbH in Duisburg where he was responsible
signal processing chip sets and started
for the design of RF circuits for cellular products.
his professional career at SIEMENS
semiconductor in Munich when Microelectronics was still Since 2017 he is a team lead for RF circuit design at Intel
on um-scale. in Munich.
Joining embedded DRAM product design group, he was
designing full custom and semicustom digital circuits and
more ‘analog’ blocks like IO drivers.
30 31■ ANALOG 2018 – Invited Talks ■ ANALOG 2018 – Invited Talks
Design Challenges and Methodology Considerations Vadim Issakov was born in the Russian
for Highly-Integrated mm-Wave Systems in Silicon- Federation in 1981
Based Technologies
He received M.Sc. degree (cum laude) in
Presenter: Vadim Issakov, Infineon Technologies, Neubiberg microwave engineering from the Techni-
The recent advances in silicon-based semiconductor pro- cal University of Munich and Ph.D. de-
cesses and packaging technologies enable high-level in- gree from the University of Paderborn,
tegration of system on chip (SoC) and system in package Germany (summa cum laude) in 2006
(SiP) solutions for millimeter-wave (mm-wave) communi- and 2010, respectively.
cation or radar applications. These solutions find growing He is a principal engineer for mm-wave circuit design at
interest due to the increasing demand for a lowest bill of Infineon Technologies AG in Neubiberg, Germany. He is a
materials. The amount of external components shall be re- technical lead of a research group working on mm-wave
duced by integrating more and more analog, digital, power circuit design in CMOS and SiGe technologies for radar and
management and RF functional blocks on the same chip, communication applications.
on a smallest chip area and at a lowest price. The demon
stration of Silicon-Germanium (SiGe) HBT or even CMOS
integrated transceiver circuits at millimeter-wave frequen-
cies has given rise to the sales volumes of classical and
emerging applications.
This talk focusses on design considerations of highly-
integrated mm-wave transceiver chipsets in silicon-based
technologies. The speaker will discuss circuit design consi-
derations and challenges related to critical building blocks.
Particularly, high sensitivity of key performance parameters
to layout parasitics at mm-wave frequencies is discussed.
Additionally, challenges related to accurate extraction of pa-
rasitics are addressed. Next, chip-package-PCB co-design
and co-simulation methodology by means of accurate EM
modelling for RF systems is presented. Furthermore, cros-
stalk mechanisms related to coupling between integrated
inductors/transformer and coupling via substrate at mm-
wave frequencies are discussed. Finally, examples of mm-
wave radar and communication systems at frequencies
above 60 GHz are presented.
32 33■ ANALOG 2018 – Invited Talks ■ ANALOG 2018 – Invited Talks
Improving Test Coverage and Eliminating Test Walter Hartong studied Electrical Engi-
Escapes Using Analog Defect Analysis neering/Microelectronics at the Universi-
ty of Hannover.
Presenter: Walter Hartong, Art Schaldenbrand,
Vladimir Zivkovic, Cadence Design Systems He worked as a research assistant at the
Institute of Microelectronic Systems and
Complex systems, like cars or planes, consist of thousands finished his PhD in Computer Science in
of sub components. If a single sub-block fails, the whole 2002.
system is at risk. Consequently, the system integrators
Since 2002, he has been with Cadence Design Systems in
have a 0-defect goal for the sub components. How can IC
Munich, initially as application engineer. His current role is
companies achieve this level of quality? While the analog
Product Engineering Architect focusing on analog simulati-
and mixed-signal components are the leading source of
on environment and verification.
test escapes that result in field failures, the lack of analog
centric tools to analyze the test coverage during design has He is one of the core drivers in the ADE Verifier develop-
made it difficult for designers to address the issue. More ment and contributes to Explorer and Assembler as well.
over, manufacturing test is a critical step to ensure quality. Walter is also interested in mixed-signal topics, analog fault
Test costs make up a significant portion of the die recurring simulation and behavioral modeling.
cost and is directly proportional to the time spent on the
tester. This demands more attention on optimizing the test Art Schaldenbrand
program and testability early in the design cycle.
Vladimir Zivkovic
Analog fault simulation has been proposed for many years
but the technology has not proliferated much so far. The
lack of analog fault models and a standard methodology
have proved to be a challenge when trying to evaluate test
coverage. The solution has been to refine the problem.
Instead of starting with hard to define analog faults, manu-
facturing defects are modelled and their effect on the cir-
cuit is simulated. Defect-oriented test evaluates the ability
of the test program to identify and eliminate manufacturing
defects. Currently the IEEE P2427 Working Group is stan-
dardizing this methodology and new tools and simulation
environments – like Cadence® Legato™ Reliability Solution
– become available commercially.
Moving forward the related functional safety question will in-
fluence the analog working environment significantly.above
60 GHz are presented.
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